1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to an embedded memory logic device using self-aligned silicide and a manufacturing method therefor.
2. Description of the Related Art
As semiconductor devices become more highly integrated, silicon on chip (SOC) devices have been introduced, in which many devices having various functions are integrated into one chip so that they interactively operate. It is more complicated and difficult to manufacture an SOC device. In order to integrate two or more devices having different functions into one chip, characteristics required for each of the devices must be realized simultaneously. Accordingly, the process becomes more complicated, and depending on the circumstances, additional processes may be required.
An embedded memory logic (EML) device, which is a type of SOC device, is obtained by integrating a memory device and a logic device into one chip. An EML device is composed of a cell array region and a logic circuit region. A plurality of memory cells are located in the cell array region and information stored in the cell array region is operated on by the logic circuit, thereby generating new information. DRAM cells or SRAM cells are widely used for the memory cells.
Effective prevention of leakage current is required as a key characteristic of the access transistors in the cell array region. Meanwhile, transistors in a peripheral circuit region need excellent current driving ability rather than leakage current prevention, since the current driving ability of these transistors determines the overall performance of the chip.
An embedded DRAM logic (EDL) device adopts DRAM cells as memory cells. In an EDL device, information charge stored in the memory cells is lost due to the leakage current. Accordingly, an operation for periodically refreshing the information is required. To improve the refresh characteristics, two main methods are used. In a first method, the capacitance of storage capacitors are increased to maintain data even though the leakage current exists. In a second method, the leakage current is reduced to maintain the stored charge.
In order to enhance the operational speed of an EDL device, a self-aligned silicide (salicide) process has been widely used. With the salicide process, a metal silicide layer having low resistivity, such as titanium silicide, is selectively formed on the gate electrode of a transistor and the source/drain region thereof.
In a conventional salicide process, titanium silicide (TiSi2) is formed on the surfaces of the gate electrodes, as well as the source/drains of NMOS transistors in the peripheral circuit portion which are heavily doped with an N-type impurity. Also, in PMOS transistors in the peripheral circuit portion, titanium silicide (TiSi2) is formed on the surfaces of the gates, as well as the source/drain which are doped with a P+ impurity. Accordingly, the resistance of the gate electrode and source/drain are reduced, which enhances current driving ability. In the same manner, titanium silicide is also formed on the surfaces of the source/drains and of the gates of NMOS transistors in the cell array region. However, this titanium silicide causes an increase of junction leakage current. The reason is as follows.
In a conventional salicide process, N+ impurities are implanted into a cell array region to form the source/drain of a memory cell transistor. However, ion-implantation damages the source/drain region. The ion-implantation damage causes crystalline defects such as dislocation, which result in increased junction leakage current between the source/drain and the P-well. When junction leakage current is increased between the P-well and the source or drain of a cell array region connected to a storage electrode of a cell capacitor, the charge stored in the storage electrode is lost quicker. Accordingly, in order to maintain the charge on the storage electrode for a predetermined time, the refresh time, i.e., the time interval between refresh cycles, must be short, and therefore, the power consumption of the device is increased accordingly.
Furthermore, a silicide layer formed on the surface of the source/drains in the cell array region causes stress in the source/drain region, which further increases crystalline defects in the heavily-doped source/drain. Therefore, the junction leakage current is increased further.